summaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
authorSylvain Lemieux <slemieux@tycoint.com>2016-04-20 16:21:00 +0300
committerVladimir Zapolskiy <vz@mleia.com>2016-04-21 22:32:35 +0300
commit961212e3fd1ee29d31f3c362f0bc854868679f63 (patch)
treef2d9f385d9d8585dda715147e3df845d6a1c53e6 /arch/arm
parent9a96877c2b08865685bb80338db7254cf76af55f (diff)
downloadlinux-961212e3fd1ee29d31f3c362f0bc854868679f63.tar.xz
ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default
The SSP0/SPI1 and SSP1/SPI2 shared pinout and should be disable by default. Board specific dts should enable them, as needed. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1b2f351e4a08..73c474610efa 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -162,32 +162,44 @@
compatible = "simple-bus";
ranges = <0x20000000 0x20000000 0x30000000>;
+ /*
+ * ssp0 and spi1 are shared pins;
+ * enable one in your board dts, as needed.
+ */
ssp0: ssp@20084000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x20084000 0x1000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SSP0>;
clock-names = "apb_pclk";
+ status = "disabled";
};
spi1: spi@20088000 {
compatible = "nxp,lpc3220-spi";
reg = <0x20088000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI1>;
+ status = "disabled";
};
+ /*
+ * ssp1 and spi2 are shared pins;
+ * enable one in your board dts, as needed.
+ */
ssp1: ssp@2008c000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x2008c000 0x1000>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SSP1>;
clock-names = "apb_pclk";
+ status = "disabled";
};
spi2: spi@20090000 {
compatible = "nxp,lpc3220-spi";
reg = <0x20090000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI2>;
+ status = "disabled";
};
i2s0: i2s@20094000 {