diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 19:40:42 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 09:45:27 +0300 |
| commit | beffa8872a3680ef804eb0320ec77037170f4686 (patch) | |
| tree | 78ccf1c4a39e666c894021a645450433d078bb0a /arch/arm | |
| parent | a0504f0880c11da301dc2b5a5135bd02376e367e (diff) | |
| download | linux-beffa8872a3680ef804eb0320ec77037170f4686.tar.xz | |
ARM: dts: r8a7793: Remove unit-address and reg from integrated cache
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: ad53f5f00b095a0d ("ARM: dts: r8a7793: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/r8a7793.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 48ce21c5e8db..38506f563b2b 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -65,9 +65,8 @@ power-domains = <&sysc R8A7793_PD_CA15_CPU1>; }; - L2_CA15: cache-controller@0 { + L2_CA15: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7793_PD_CA15_SCU>; cache-unified; cache-level = <2>; |