diff options
| author | Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> | 2014-09-22 14:08:11 +0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-11-23 10:08:05 +0300 |
| commit | 9c42fa1d94e5b0d0ed11f5b9762a9b7acb1fcf15 (patch) | |
| tree | 9a3b612e087e684949e697df6ee1d78865b4bf45 /arch/arm | |
| parent | a1d00bc592ece539296e0104107877700819c32c (diff) | |
| download | linux-9c42fa1d94e5b0d0ed11f5b9762a9b7acb1fcf15.tar.xz | |
ARM: dts: vf610-colibri: Add PWM support
The Colibri standard defines four pins as PWM outputs, two of them (PWM
A and C) are routed to FTM instance 0 and the other two (PWM B and D)
are routed to FTM instance 1. Hence enable both FTM instances for the
Colibri module and mux the four pins accordingly.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/vf610-colibri-eval-v3.dts | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/vf610-colibri.dtsi | 24 |
2 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts index 7fb306679341..00f63d936aab 100644 --- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts @@ -33,6 +33,14 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi index 0cd83434b073..1f73c1c824e5 100644 --- a/arch/arm/boot/dts/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -44,6 +44,16 @@ arm,tag-latency = <3 2 3>; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -97,6 +107,20 @@ >; }; + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1182 + VF610_PAD_PTB1__FTM0_CH1 0x1182 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + VF610_PAD_PTB8__FTM1_CH0 0x1182 + VF610_PAD_PTB9__FTM1_CH1 0x1182 + >; + }; + pinctrl_uart0: uart0grp { fsl,pins = < VF610_PAD_PTB10__UART0_TX 0x21a2 |