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| author | Marc Zyngier <maz@kernel.org> | 2019-12-24 14:10:28 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-01-22 17:22:19 +0300 |
| commit | 5e5168461c22c8738d31d4ee12a5cbc2ab0aa440 (patch) | |
| tree | 1bce63dc769e715e017ef483ecf04b8414d4b947 /arch/arm | |
| parent | f2d834092ee276610ccb6637e5109b61fc79ab89 (diff) | |
| download | linux-5e5168461c22c8738d31d4ee12a5cbc2ab0aa440.tar.xz | |
irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation
GICv4.1 defines a new VPE table that is potentially shared between
both the ITSs and the redistributors, following complicated affinity
rules.
To make things more confusing, the programming of this table at
the redistributor level is reusing the GICv4.0 GICR_VPROPBASER register
for something completely different.
The code flow is somewhat complexified by the need to respect the
affinities required by the HW, meaning that tables can either be
inherited from a previously discovered ITS or redistributor.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Link: https://lore.kernel.org/r/20191224111055.11836-6-maz@kernel.org
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch_gicv3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h index fa50bb04f580..b5752f0e8936 100644 --- a/arch/arm/include/asm/arch_gicv3.h +++ b/arch/arm/include/asm/arch_gicv3.h @@ -10,6 +10,7 @@ #ifndef __ASSEMBLY__ #include <linux/io.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include <asm/barrier.h> #include <asm/cacheflush.h> #include <asm/cp15.h> @@ -327,6 +328,7 @@ static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr) /* * GITS_VPROPBASER - hi and lo bits may be accessed independently. */ +#define gits_read_vpropbaser(c) __gic_readq_nonatomic(c) #define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c) /* |