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| author | Jonathan Marek <jonathan@marek.ca> | 2018-12-04 18:17:00 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-12-10 05:03:08 +0300 |
| commit | 006303d6ba8edda0bbb2c2a271c2faa2968f18c8 (patch) | |
| tree | 6f3a834d392c02486551b490c84bb49dbe2e5fa8 /arch/arm | |
| parent | 47853f18b63557740ef730cb212035fae8d13c88 (diff) | |
| download | linux-006303d6ba8edda0bbb2c2a271c2faa2968f18c8.tar.xz | |
ARM: dts: imx5: add gpu nodes
This adds the gpu nodes for the adreno 200 GPU on iMX51 and iMX53, now
supported by the freedreno driver.
The compatible for the iMX51 uses a patchid of 1, which is used by drm/msm
driver to identify the smaller 128KiB GMEM size.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/imx51.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 10 |
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 7651bedabdfb..a5ee25cedc10 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -121,6 +121,16 @@ reg = <0x1ffe0000 0x20000>; }; + gpu: gpu@30000000 { + compatible = "amd,imageon-200.1", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; + ipu: ipu@40000000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index a9804c08e6a8..b3300300aabe 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -200,6 +200,16 @@ }; }; + gpu: gpu@30000000 { + compatible = "amd,imageon-200.0", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; + aips@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; |