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author | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2017-06-28 23:14:12 +0300 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-07-03 00:51:20 +0300 |
commit | 769b461fc0c0451bacf75826d5830fc07c5a57e4 (patch) | |
tree | 355872ec8be7404a7677c77b9cd2a048eaa1d5ad /arch/arm64 | |
parent | 1ee4d93d5037c9247a81431b563b03e436e3f7b6 (diff) | |
download | linux-769b461fc0c0451bacf75826d5830fc07c5a57e4.tar.xz |
arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()
With the introduction of struct pci_host_bridge.map_irq pointer it is
possible to assign IRQs for all devices originating from a PCI host bridge
at probe time; this is implemented through pci_assign_irq() that relies on
the struct pci_host_bridge.map_irq pointer to map IRQ for a given device.
The benefits this brings are twofold:
- the IRQ for a device is assigned once at probe time
- the IRQ assignment works also for hotplugged devices
With all DT based PCI host bridges converted to the struct
pci_host_bridge.{map/swizzle}_irq hooks mechanism the DT IRQ allocation in
ARM64 pcibios_alloc_irq() is now redundant and can be removed.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/kernel/pci.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 4f0e3ebfea4b..efcc351c518f 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -39,20 +39,18 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res, return res->start; } +#ifdef CONFIG_ACPI /* * Try to assign the IRQ number when probing a new device */ int pcibios_alloc_irq(struct pci_dev *dev) { - if (acpi_disabled) - dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); -#ifdef CONFIG_ACPI - else - return acpi_pci_irq_enable(dev); -#endif + if (!acpi_disabled) + acpi_pci_irq_enable(dev); return 0; } +#endif /* * raw_pci_read/write - Platform-specific PCI config space access. |