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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2014-08-05 13:25:55 +0400 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-08-18 22:47:03 +0400 |
| commit | a3a80544acb3dfa97d43b8eee1332fe1fca7fe51 (patch) | |
| tree | 3ca111e74a6addb43b403bd43cfb73bc0b3aab13 /arch/arm64 | |
| parent | 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9 (diff) | |
| download | linux-a3a80544acb3dfa97d43b8eee1332fe1fca7fe51.tar.xz | |
arm64: fix typo in I-cache policy detection
This removes an unfortunately placed semi-colon resulting in all instruction
caches being classified as AIVIVT.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kernel/cpuinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index f798f66634af..177169623026 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -49,7 +49,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) if (l1ip != ICACHE_POLICY_PIPT) set_bit(ICACHEF_ALIASING, &__icache_flags); - if (l1ip == ICACHE_POLICY_AIVIVT); + if (l1ip == ICACHE_POLICY_AIVIVT) set_bit(ICACHEF_AIVIVT, &__icache_flags); pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); |