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| author | Catalin Marinas <catalin.marinas@arm.com> | 2014-03-24 14:35:35 +0400 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-03-24 14:35:35 +0400 |
| commit | 196adf2f3015eacac0567278ba538e3ffdd16d0e (patch) | |
| tree | 2dc6514b3263a9f3ed69b3b0ff34ef908afa5af7 /arch/arm64/mm | |
| parent | 214fdbe74a096c3aeb7af81d7900e2ab966b10d6 (diff) | |
| download | linux-196adf2f3015eacac0567278ba538e3ffdd16d0e.tar.xz | |
arm64: Remove pgprot_dmacoherent()
Since this macro is identical to pgprot_writecombine() and is only used
in a single place, remove it completely to avoid confusion. On ARMv7+
processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a.
writecombine) to avoid mismatched hardware attribute aliases (with the
kernel linear mapping as Normal Cacheable).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
| -rw-r--r-- | arch/arm64/mm/dma-mapping.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 5bba6be1a3f1..0ba347e59f06 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -33,10 +33,8 @@ EXPORT_SYMBOL(dma_ops); static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot, bool coherent) { - if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) + if (!coherent || dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) return pgprot_writecombine(prot); - else if (!coherent) - return pgprot_dmacoherent(prot); return prot; } |