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| author | Will Deacon <will.deacon@arm.com> | 2018-01-29 14:59:57 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-02-07 01:53:21 +0300 |
| commit | fa0465fc07c2f9f47bd1198ab368d341bd7c7e4e (patch) | |
| tree | 1015b0bb0f69b0b88e21af1c15924c7102871321 /arch/arm64/kernel/head.S | |
| parent | 6dc52b15c4a48052ade2529d639eee401d76e469 (diff) | |
| download | linux-fa0465fc07c2f9f47bd1198ab368d341bd7c7e4e.tar.xz | |
arm64: assembler: Change order of macro arguments in phys_to_ttbr
Since AArch64 assembly instructions take the destination register as
their first operand, do the same thing for the phys_to_ttbr macro.
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel/head.S')
| -rw-r--r-- | arch/arm64/kernel/head.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index ba3ab04788dc..341649c08337 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -776,8 +776,8 @@ ENTRY(__enable_mmu) update_early_cpu_boot_status 0, x1, x2 adrp x1, idmap_pg_dir adrp x2, swapper_pg_dir - phys_to_ttbr x1, x3 - phys_to_ttbr x2, x4 + phys_to_ttbr x3, x1 + phys_to_ttbr x4, x2 msr ttbr0_el1, x3 // load TTBR0 msr ttbr1_el1, x4 // load TTBR1 isb |