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| author | Catalin Marinas <catalin.marinas@arm.com> | 2020-07-31 20:09:50 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2020-07-31 20:09:50 +0300 |
| commit | 18aa3bd58b1428d1927fe11f85ad444423d4fc59 (patch) | |
| tree | 40171776fd498d9ae9378c9559fcada83c92ee17 /arch/arm64/include/asm/sysreg.h | |
| parent | 4557062da7ebfa9236af83fcb4323a1838ae533e (diff) | |
| parent | d1d3aa98b1d4826a19adfefb69b96142a0cac633 (diff) | |
| download | linux-18aa3bd58b1428d1927fe11f85ad444423d4fc59.tar.xz | |
Merge branch 'for-next/tlbi' into for-next/core
* for-next/tlbi:
: Support for TTL (translation table level) hint in the TLB operations
arm64: tlb: Use the TLBI RANGE feature in arm64
arm64: enable tlbi range instructions
arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature
arm64: tlb: don't set the ttl value in flush_tlb_page_nosync
arm64: Shift the __tlbi_level() indentation left
arm64: tlb: Set the TTL field in flush_*_tlb_range
arm64: tlb: Set the TTL field in flush_tlb_range
tlb: mmu_gather: add tlb_flush_*_range APIs
arm64: Add tlbi_user_level TLB invalidation helper
arm64: Add level-hinted TLB invalidation helper
arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors
arm64: Detect the ARMv8.4 TTL feature
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 0372262489ee..554a7e8ecb07 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -617,6 +617,9 @@ #define ID_AA64ISAR0_SHA1_SHIFT 8 #define ID_AA64ISAR0_AES_SHIFT 4 +#define ID_AA64ISAR0_TLB_RANGE_NI 0x0 +#define ID_AA64ISAR0_TLB_RANGE 0x2 + /* id_aa64isar1 */ #define ID_AA64ISAR1_I8MM_SHIFT 52 #define ID_AA64ISAR1_DGH_SHIFT 48 |