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| author | Will Deacon <will.deacon@arm.com> | 2018-09-13 15:30:45 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-07 20:27:55 +0300 |
| commit | 5ef3fe4cecdf82fdd71ce78988403963d01444d4 (patch) | |
| tree | 937f28f9e3beea1a63e0d21c4c95bf604af3ade2 /arch/arm64/include/asm/cpucaps.h | |
| parent | 396244692232fcf0881cb6ba2404be2906f47681 (diff) | |
| download | linux-5ef3fe4cecdf82fdd71ce78988403963d01444d4.tar.xz | |
arm64: Avoid redundant type conversions in xchg() and cmpxchg()
Our atomic instructions (either LSE atomics of LDXR/STXR sequences)
natively support byte, half-word, word and double-word memory accesses
so there is no need to mask the data register prior to being stored.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
0 files changed, 0 insertions, 0 deletions