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| author | Michal Simek <michal.simek@xilinx.com> | 2021-01-21 15:36:06 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-02-01 12:40:36 +0300 |
| commit | b0f89cf5b62784823e1661780e846ea58d0816ce (patch) | |
| tree | 04171cc02635a1d2ce4a4059fa43f2b55c2f6817 /arch/arm64/boot/dts/xilinx | |
| parent | 7b6714b3edeb98c6903cb8d74c7528fc3fc70538 (diff) | |
| download | linux-b0f89cf5b62784823e1661780e846ea58d0816ce.tar.xz | |
arm64: dts: zynqmp: Add DisplayPort subsystem
Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/4d978aef852cacdfb35aa8e50d648a787e73b90c.1611232558.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 22 |
2 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index c676afc95f6d..cf5295224750 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -231,3 +231,9 @@ &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; + +&zynqmp_dpsub { + clocks = <&zynqmp_clk TOPSW_LSBUS>, + <&zynqmp_clk DP_AUDIO_REF>, + <&zynqmp_clk DP_VIDEO_REF>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index f12cd24adbee..a3b391d18787 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -12,6 +12,7 @@ * the License, or (at your option) any later version. */ +#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> @@ -857,5 +858,26 @@ clock-names = "axi_clk"; #dma-cells = <1>; }; + + zynqmp_dpsub: display@fd4a0000 { + compatible = "xlnx,zynqmp-dpsub-1.7"; + status = "disabled"; + reg = <0x0 0xfd4a0000 0x0 0x1000>, + <0x0 0xfd4aa000 0x0 0x1000>, + <0x0 0xfd4ab000 0x0 0x1000>, + <0x0 0xfd4ac000 0x0 0x1000>; + reg-names = "dp", "blend", "av_buf", "aud"; + interrupts = <0 119 4>; + interrupt-parent = <&gic>; + clock-names = "dp_apb_clk", "dp_aud_clk", + "dp_vtc_pixel_clk_in"; + power-domains = <&zynqmp_firmware PD_DP>; + resets = <&zynqmp_reset ZYNQMP_RESET_DP>; + dma-names = "vid0", "vid1", "vid2", "gfx0"; + dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, + <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, + <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, + <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + }; }; }; |