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| author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2022-09-13 07:23:21 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-09-28 23:41:48 +0300 |
| commit | 5381a96cd9c4247eafb2dfcfccf491d0bba2f5ca (patch) | |
| tree | cb8a2a7545007dd2ae5a8dd80ab9d587daff3bcf /arch/arm64/boot/dts/socionext | |
| parent | d93ecbf56946640b3746dcd7b0fe4c808bf2b580 (diff) | |
| download | linux-5381a96cd9c4247eafb2dfcfccf491d0bba2f5ca.tar.xz | |
arm64: dts: uniphier: Add L2 cache node
Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy
information because the following warning was issued.
cacheinfo: Unable to detect cache hierarchy for CPU 0
Early cacheinfo failed, ret = -2
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-11-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/socionext')
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 12 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 8 |
3 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 525bff79efea..1c76b4375b2e 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -36,6 +36,7 @@ reg = <0 0x000>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; }; @@ -45,8 +46,13 @@ reg = <0 0x001>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; }; + + l2: l2-cache { + compatible = "cache"; + }; }; cluster0_opp: opp-table { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 938753ded7c0..9308458f9611 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -46,6 +46,7 @@ reg = <0 0x000>; clocks = <&sys_clk 32>; enable-method = "psci"; + next-level-cache = <&a72_l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -56,6 +57,7 @@ reg = <0 0x001>; clocks = <&sys_clk 32>; enable-method = "psci"; + next-level-cache = <&a72_l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -66,6 +68,7 @@ reg = <0 0x100>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&a53_l2>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; }; @@ -76,9 +79,18 @@ reg = <0 0x101>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&a53_l2>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; }; + + a72_l2: l2-cache0 { + compatible = "cache"; + }; + + a53_l2: l2-cache1 { + compatible = "cache"; + }; }; cluster0_opp: opp-table-0 { diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index f10685625b6a..b0c29510a7da 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -43,6 +43,7 @@ reg = <0 0x000>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -53,6 +54,7 @@ reg = <0 0x001>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -63,6 +65,7 @@ reg = <0 0x002>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -73,9 +76,14 @@ reg = <0 0x003>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; + + l2: l2-cache { + compatible = "cache"; + }; }; cluster0_opp: opp-table { |