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| author | Rocky Hao <rocky.hao@rock-chips.com> | 2017-08-04 11:06:15 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-08-11 18:14:20 +0300 |
| commit | 87e0d607e5a4f1eed67f916b6f19420bbafbca59 (patch) | |
| tree | df40daa4cce4f6460cc79cee3e0ae4687e781051 /arch/arm64/boot/dts/rockchip/rk3328.dtsi | |
| parent | 20590de2802155e65968e7569587f3dd29218d50 (diff) | |
| download | linux-87e0d607e5a4f1eed67f916b6f19420bbafbca59.tar.xz | |
arm64: dts: rockchip: add thermal nodes for rk3328 SoC
add thermal zone and dynamic CPU power coefficients for rk3328
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3328.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3328.dtsi | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 5cc186b3c31b..e6da0cee1241 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/power/rk3328-power.h> #include <dt-bindings/soc/rockchip,boot-mode.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "rockchip,rk3328"; @@ -74,6 +75,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; @@ -84,6 +87,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; @@ -94,6 +98,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; @@ -104,6 +109,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; @@ -400,6 +406,43 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; }; + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + + }; + tsadc: tsadc@ff250000 { compatible = "rockchip,rk3328-tsadc"; reg = <0x0 0xff250000 0x0 0x100>; |