diff options
| author | Krishna Kurapati <quic_kriskura@quicinc.com> | 2024-01-25 21:59:18 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-01-28 01:42:02 +0300 |
| commit | 2c6597c72e9722ac020102d5af40126df0437b82 (patch) | |
| tree | ebd82d8a6319a855333ae52adf3610b86c1ff6cc /arch/arm64/boot/dts/qcom/sm6125.dtsi | |
| parent | b5e25ded2721ad75456eac21acb5b2fc6fa5d2bb (diff) | |
| download | linux-2c6597c72e9722ac020102d5af40126df0437b82.tar.xz | |
arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.
In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.
Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.
Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6125.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 1dd3a4056e26..00a2e0980163 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1185,9 +1185,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; qcom,select-utmi-as-pipe-clk; |