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authorAndre Przywara <andre.przywara@arm.com>2020-09-07 15:18:30 +0300
committerOlof Johansson <olof@lixom.net>2020-10-03 22:56:03 +0300
commitfc772314a3683ab3f19aa68a660a0f70a8e836a4 (patch)
tree90e8349e7535afc9cb802bf04e0ee87f031cd896 /arch/arm64/boot/dts/lg/lg1313.dtsi
parentf6320e326f401e077bf7a042db0740c441ca0c8e (diff)
downloadlinux-fc772314a3683ab3f19aa68a660a0f70a8e836a4.tar.xz
arm64: dts: lg: Fix SP805 clocks
The SP805 DT binding requires two clocks to be specified, but the two LG platform DTs currently only specify one clock. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux (and U-Boot) SP805 driver would use the first clock to derive the actual watchdog counter frequency. Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Link: https://lore.kernel.org/r/20200907121831.242281-6-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot/dts/lg/lg1313.dtsi')
-rw-r--r--arch/arm64/boot/dts/lg/lg1313.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index ac23592ab011..2cea5b18aac7 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -141,8 +141,8 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xfd200000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_bus>;
- clock-names = "apb_pclk";
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "wdog_clk", "apb_pclk";
};
uart0: serial@fe000000 {
compatible = "arm,pl011", "arm,primecell";