diff options
| author | Rob Herring <robh@kernel.org> | 2021-09-28 22:21:54 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-10-05 09:00:03 +0300 |
| commit | 869f0ec048dc8fd88c0b2003373bd985795179fb (patch) | |
| tree | b2d8b29b060651b5d5fcf87b9d61e76ec5f722ce /arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | |
| parent | caa355c53ba4c3c643aca917b707fb6a3ff5e6fa (diff) | |
| download | linux-869f0ec048dc8fd88c0b2003373bd985795179fb.tar.xz | |
arm64: dts: freescale: Fix 'interrupt-map' parent address cells
The 'interrupt-map' in several Layerscape SoCs is malformed. The
'#address-cells' size of the parent interrupt controller (the GIC) is not
accounted for.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Li Yang <leoyang.li@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 605072317243..f891ef6a3754 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -241,18 +241,18 @@ interrupt-controller; reg = <0x14 4>; interrupt-map = - <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + <0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0xffffffff 0x0>; }; }; |