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| author | Samuel Holland <samuel@sholland.org> | 2022-08-30 05:08:24 +0300 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2022-09-08 23:00:34 +0300 |
| commit | 5db5663cdf369b3575dae464cdcda0233ab19f44 (patch) | |
| tree | 35cbf4c5c5600502c7008665310d31bb3f3df605 /arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | |
| parent | 7072784d97b2b140a9e5507a29fcbc9b70dfc343 (diff) | |
| download | linux-5db5663cdf369b3575dae464cdcda0233ab19f44.tar.xz | |
arm64: dts: allwinner: a100: Add I2C DMA requests
The I2C controllers in the A100 SoC are all connected to the DMA engine.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220830020824.62288-4-samuel@sholland.org
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index 5453a3bb7d81..97e3e6907acd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -221,6 +221,8 @@ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -234,6 +236,8 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -247,6 +251,8 @@ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -260,6 +266,8 @@ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -337,6 +345,8 @@ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB2_I2C0>; resets = <&r_ccu RST_R_APB2_I2C0>; + dmas = <&dma 50>, <&dma 50>; + dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&r_i2c0_pins>; status = "disabled"; @@ -352,6 +362,8 @@ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB2_I2C1>; resets = <&r_ccu RST_R_APB2_I2C1>; + dmas = <&dma 51>, <&dma 51>; + dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&r_i2c1_pins>; status = "disabled"; |