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author | Will Deacon <will@kernel.org> | 2022-03-14 22:00:44 +0300 |
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committer | Will Deacon <will@kernel.org> | 2022-03-14 22:00:44 +0300 |
commit | cd92fdfcfa390ee5dac16f4b533b0c0adc6aff03 (patch) | |
tree | bcc3dcdeeb682aff9c2a75ee61c92f985e4c1c9f /arch/arm64/Kconfig | |
parent | b523d6b80fbcf45f64f5010424a273c32df79e7a (diff) | |
parent | f90205b95368ee2b56fc523abda6c4d514901d9b (diff) | |
download | linux-cd92fdfcfa390ee5dac16f4b533b0c0adc6aff03.tar.xz |
Merge branch 'for-next/errata' into for-next/core
* for-next/errata:
arm64: Add cavium_erratum_23154_cpus missing sentinel
irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
Diffstat (limited to 'arch/arm64/Kconfig')
-rw-r--r-- | arch/arm64/Kconfig | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b55c11796fad..1d1b5c0b157c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -891,13 +891,17 @@ config CAVIUM_ERRATUM_23144 If unsure, say Y. config CAVIUM_ERRATUM_23154 - bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" + bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" default y help - The gicv3 of ThunderX requires a modified version for + The ThunderX GICv3 implementation requires a modified version for reading the IAR status to ensure data synchronization (access to icc_iar1_el1 is not sync'ed before and after). + It also suffers from erratum 38545 (also present on Marvell's + OcteonTX and OcteonTX2), resulting in deactivated interrupts being + spuriously presented to the CPU interface. + If unsure, say Y. config CAVIUM_ERRATUM_27456 |