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| author | Vladimir Murzin <vladimir.murzin@arm.com> | 2017-04-24 12:41:53 +0300 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-04-26 12:59:36 +0300 |
| commit | b70cd406d7fe9976962d621d8c60d324eb47d284 (patch) | |
| tree | 98aa98df6b8f749605d72cc6f74ace87d830152b /arch/arm/mm | |
| parent | 6f05d0761af612e04572ba4d65b4c0274a88444f (diff) | |
| download | linux-b70cd406d7fe9976962d621d8c60d324eb47d284.tar.xz | |
ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode
According to ARMv7 ARM, when exception is taken content of r0-r3, r12
is unknown (see ExceptionTaken() pseudocode). Even though existent
implementations keep these register unchanged, preserve them to be in
line with architecture.
Reported-by: Dobromir Stefanov <dobromir.stefanov@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7m.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 8dea61640cc1..11ae6b847ad0 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -135,9 +135,11 @@ __v7m_setup_cont: dsb mov r6, lr @ save LR ldr sp, =init_thread_union + THREAD_START_SP + stmia sp, {r0-r3, r12} cpsie i svc #0 1: cpsid i + ldmia sp, {r0-r3, r12} str r5, [r12, #11 * 4] @ restore the original SVC vector entry mov lr, r6 @ restore LR |