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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-07-05 12:01:13 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-07-19 14:44:06 +0400 |
| commit | 4348810a241a330d3d143d62d7c988ec8b2e6629 (patch) | |
| tree | 057e8799eb71e35702f39dc276bceb5d93567000 /arch/arm/mm/tlb-v7.S | |
| parent | eb96c925152fc289311e5d7e956b919e9b60ab53 (diff) | |
| download | linux-4348810a241a330d3d143d62d7c988ec8b2e6629.tar.xz | |
ARM: btc: avoid invalidating the branch target cache on kernel TLB maintanence
Kernel space needs very little in the way of BTC maintanence as most
mappings which are created and destroyed are non-executable, and so
could never enter the instruction stream.
The case which does warrant BTC maintanence is when a module is loaded.
This creates a new executable mapping, but at that point the pages have
not been initialized with code and data, so at that point they contain
unpredictable information. Invalidating the BTC at this stage serves
little useful purpose.
Before we execute module code, we call flush_icache_range(), which deals
with the BTC maintanence requirements. This ensures that we have a BTC
maintanence operation before we execute code via the newly created
mapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/tlb-v7.S')
| -rw-r--r-- | arch/arm/mm/tlb-v7.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index 53cd5b454673..86bb71664508 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S @@ -48,9 +48,6 @@ ENTRY(v7wbi_flush_user_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b - mov ip, #0 - ALT_SMP(mcr p15, 0, ip, c7, c1, 6) @ flush BTAC/BTB Inner Shareable - ALT_UP(mcr p15, 0, ip, c7, c5, 6) @ flush BTAC/BTB dsb mov pc, lr ENDPROC(v7wbi_flush_user_tlb_range) @@ -75,9 +72,6 @@ ENTRY(v7wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b - mov r2, #0 - ALT_SMP(mcr p15, 0, r2, c7, c1, 6) @ flush BTAC/BTB Inner Shareable - ALT_UP(mcr p15, 0, r2, c7, c5, 6) @ flush BTAC/BTB dsb isb mov pc, lr |