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| author | Catalin Marinas <catalin.marinas@arm.com> | 2007-05-09 01:27:46 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-05-09 01:55:53 +0400 |
| commit | bbe888864ec32435e93923c40b9d6ce2bb73844b (patch) | |
| tree | db607482fe5898da9a599368d0bbe579a56b272c /arch/arm/mm/proc-macros.S | |
| parent | 5b94f675f57e4ff16c8fda09088d7480a84dcd91 (diff) | |
| download | linux-bbe888864ec32435e93923c40b9d6ce2bb73844b.tar.xz | |
[ARM] armv7: add support for ARMv7 cores.
This patch adds support for the ARMv7 cores.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 9e2c89eb2115..b13150052a76 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -59,3 +59,15 @@ .word \ucset #endif .endm + +/* + * cache_line_size - get the cache line size from the CSIDR register + * (available on ARMv7+). It assumes that the CSSR register was configured + * to access the L1 data cache CSIDR. + */ + .macro dcache_line_size, reg, tmp + mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR + and \tmp, \tmp, #7 @ cache line size encoding + mov \reg, #16 @ size offset + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm |