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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-08-26 23:28:52 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-09-21 02:33:36 +0400 |
| commit | e8ce0eb5e2254b85415e4b58e73f24a5d13846a1 (patch) | |
| tree | 26aaee04d5a4bb872eea215f65073825258ecd76 /arch/arm/mm/proc-arm926.S | |
| parent | f5fa68d9674156ddaafa12a058ccc93c8866d5f9 (diff) | |
| download | linux-e8ce0eb5e2254b85415e4b58e73f24a5d13846a1.tar.xz | |
ARM: pm: preallocate a page table for suspend/resume
Preallocate a page table and setup an identity mapping for the MMU
enable code. This means we don't have to "borrow" a page table to
do this, avoiding complexities with L2 cache coherency.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm926.S')
| -rw-r--r-- | arch/arm/mm/proc-arm926.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index cd8f79c3a282..48add848b997 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -415,10 +415,6 @@ ENTRY(cpu_arm926_do_resume) mcr p15, 0, r5, c3, c0, 0 @ Domain ID mcr p15, 0, r6, c2, c0, 0 @ TTB address mov r0, r7 @ control register - mov r2, r6, lsr #14 @ get TTB0 base - mov r2, r2, lsl #14 - ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ - PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE b cpu_resume_mmu ENDPROC(cpu_arm926_do_resume) #endif |