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| author | Catalin Marinas <catalin.marinas@arm.com> | 2011-11-22 21:30:31 +0400 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 14:30:40 +0400 |
| commit | f7b8156d150f7383b42622a9219b230b36435b4a (patch) | |
| tree | c06e0ed558f7a9e106920a9f3acbb6bed15017bf /arch/arm/mm/fault.h | |
| parent | c9f27f1026f55b543df260ad8ab84a7bdab7792f (diff) | |
| download | linux-f7b8156d150f7383b42622a9219b230b36435b4a.tar.xz | |
ARM: LPAE: Add fault handling support
The DFSR and IFSR register format is different when LPAE is enabled. In
addition, DFSR and IFSR have similar definitions for the fault type.
This modifies the fault code to correctly handle the new format.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/fault.h')
| -rw-r--r-- | arch/arm/mm/fault.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index 25b45c105be2..cf08bdfbe0d6 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -8,11 +8,19 @@ #define FSR_WRITE (1 << 11) #define FSR_FS4 (1 << 10) #define FSR_FS3_0 (15) +#define FSR_FS5_0 (0x3f) +#ifdef CONFIG_ARM_LPAE +static inline int fsr_fs(unsigned int fsr) +{ + return fsr & FSR_FS5_0; +} +#else static inline int fsr_fs(unsigned int fsr) { return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6; } +#endif void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs); unsigned long search_exception_table(unsigned long addr); |