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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-10-25 01:36:36 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-10-29 22:13:09 +0300 |
| commit | df71dfd4ca01130f98d9dbfab76c440d72a177c6 (patch) | |
| tree | 5050d23a67be5fc5fabd4e6d96ac89786fb2a9c9 /arch/arm/mm/context.c | |
| parent | 657e12fd388899502d47f9f6f9d276ec9ced8add (diff) | |
| download | linux-df71dfd4ca01130f98d9dbfab76c440d72a177c6.tar.xz | |
ARM: Fix errata 411920 workarounds
Errata 411920 indicates that any "invalidate entire instruction cache"
operation can fail if the right conditions are present. This is not
limited just to those operations in flush.c, but elsewhere. Place the
workaround in the already existing __flush_icache_all() function
instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/context.c')
| -rw-r--r-- | arch/arm/mm/context.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 6bda76a43199..a9e22e31eaa1 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -50,10 +50,7 @@ void __new_context(struct mm_struct *mm) isb(); flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { - asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" - "mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n" - : - : "r" (0)); + __flush_icache_all(); dsb(); } } |