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| author | Jiri Kosina <jkosina@suse.cz> | 2011-05-18 19:06:31 +0400 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2011-05-18 19:06:49 +0400 |
| commit | 6b7b8e488bbdedeccabdd001a78ffcbe43bb8a3a (patch) | |
| tree | f2f77cc31b4548745778fca6a51b09e1d8a49804 /arch/arm/mm/cache-v7.S | |
| parent | b50f315cbb865079a16a12fd9ae6083f98fd592c (diff) | |
| parent | c1d10d18c542278b7fbc413c289d3cb6219da6b3 (diff) | |
| download | linux-6b7b8e488bbdedeccabdd001a78ffcbe43bb8a3a.tar.xz | |
Merge branch 'master' into upstream.
This is sync with Linus' tree to receive KEY_IMAGES definition
that went in through input tree.
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 6136e68ce953..dc18d81ef8ce 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all) * Flush the entire cache system. * The data cache flush is now achieved using atomic clean / invalidates * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. + * maintenance instructions. * The instruction cache can still be invalidated back to the point of * unification in a single instruction. * |