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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-05-21 18:15:24 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-05-21 18:15:24 +0400 |
| commit | 4175160b065e74572819a320dcd34129224a4e1c (patch) | |
| tree | 3298e2c9a7c7db33bf28617875e5429e17eec61c /arch/arm/mm/cache-v4wb.S | |
| parent | ddf90a2ff2c4a9da99acc898a4afeab3e4251fcd (diff) | |
| parent | 0ec8e7aa8f63f0cacd545fcd7f40f93fde2c0e6e (diff) | |
| download | linux-4175160b065e74572819a320dcd34129224a4e1c.tar.xz | |
Merge branch 'misc' into for-linus
Conflicts:
arch/arm/kernel/ptrace.c
Diffstat (limited to 'arch/arm/mm/cache-v4wb.S')
| -rw-r--r-- | arch/arm/mm/cache-v4wb.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 4f2c14151ccb..8f1eeae340c8 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -167,9 +167,9 @@ ENTRY(v4wb_coherent_user_range) add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b - mov ip, #0 - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache - mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr |