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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-19 16:22:34 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-30 03:50:28 +0400
commit2c4133c5d0e98ea5c7faca780e2b846d10f430c8 (patch)
treeb4f5157e92e151eac1988e07862fd9cd9fc0db69 /arch/arm/mach-zynq
parentb28dd4ac66de15c48b00184b63180094f2f7fb45 (diff)
downloadlinux-2c4133c5d0e98ea5c7faca780e2b846d10f430c8.tar.xz
ARM: l2c: zynq: remove cache size override
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-zynq')
-rw-r--r--arch/arm/mach-zynq/common.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 6fcc584c1a11..1e617a6dedc3 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -70,7 +70,7 @@ static void __init zynq_init_machine(void)
/*
* 64KB way size, 8-way associativity, parity disabled
*/
- l2x0_of_init(0x02060000, 0xF0F0FFFF);
+ l2x0_of_init(0x02000000, 0xf0ffffff);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);