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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2014-09-03 01:19:09 +0400
committerMichal Simek <michal.simek@xilinx.com>2014-09-16 14:55:07 +0400
commit0beb2bd36f6216f455363f47f8ba32fdf26667fb (patch)
treefb371f2b3d8c5e23b81cd714d697042227c3dc6b /arch/arm/mach-zynq/common.h
parent36ad5ae6dea7ae6abbb7bdf25078e7d1dabcecad (diff)
downloadlinux-0beb2bd36f6216f455363f47f8ba32fdf26667fb.tar.xz
ARM: zynq: PM: Enable DDR clock stop
The DDR controller can detect idle periods and leverage low power features clock stop. When new requests occur, the DDRC resumes normal operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynq/common.h')
-rw-r--r--arch/arm/mach-zynq/common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 596ef0b5067c..0edbb6997b1c 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -40,6 +40,8 @@ extern void __iomem *zynq_scu_base;
/* Hotplug */
extern void zynq_platform_cpu_die(unsigned int cpu);
+void zynq_pm_late_init(void);
+
static inline void zynq_core_pm_init(void)
{
/* A9 clock gating */