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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-04 19:01:03 +0300 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-14 22:21:40 +0300 |
| commit | 384895330e0f3954d9478fd0853145f9c169df12 (patch) | |
| tree | c90f70f4e070b640a1f1f2a76cf4acf864354093 /arch/arm/mach-ux500/platsmp.c | |
| parent | b580b899dd05a007ad232ee49a07b32d91876462 (diff) | |
| download | linux-384895330e0f3954d9478fd0853145f9c169df12.tar.xz | |
ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init
We don't need to re-pass the base address for the CPU interfaces to the
GIC for secondary CPUs, as it will never be different from the boot CPU
- and even if it was, we'd overwrite the boot CPU's base address.
Get rid of this argument, and rename to gic_secondary_init().
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ux500/platsmp.c')
| -rw-r--r-- | arch/arm/mach-ux500/platsmp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 9e4c678de785..b5077b4c419f 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); + gic_secondary_init(0); /* * let the primary processor know we're out of the |