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| author | Stephen Warren <swarren@nvidia.com> | 2013-01-28 22:22:46 +0400 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 22:22:46 +0400 |
| commit | ee059485175b21079d3639f167980d354afb3d4b (patch) | |
| tree | 30bf32ec57ba915d31348c1b603481baf42c81dd /arch/arm/mach-tegra | |
| parent | 1d328606c66b9bb1c0552f585943d596f37ae3b9 (diff) | |
| parent | 80d9375617f7544f7475e7f07003a08930559d43 (diff) | |
| download | linux-ee059485175b21079d3639f167980d354afb3d4b.tar.xz | |
Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114
Conflicts:
arch/arm/mach-tegra/platsmp.c
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/platsmp.c | 19 |
1 files changed, 2 insertions, 17 deletions
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 3ec7fc487857..2ff68a47099d 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -38,7 +38,6 @@ extern void tegra_secondary_startup(void); static cpumask_t tegra_cpu_init_mask; -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) @@ -177,23 +176,8 @@ done: return status; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ static void __init tegra_smp_init_cpus(void) { - unsigned int i, ncores = scu_get_core_count(scu_base); - - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - set_smp_cross_call(gic_raise_softirq); } @@ -202,7 +186,8 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) /* Always mark the boot CPU (CPU0) as initialized. */ cpumask_set_cpu(0, &tegra_cpu_init_mask); - scu_enable(scu_base); + if (scu_a9_has_base()) + scu_enable(IO_ADDRESS(scu_a9_get_base())); } struct smp_operations tegra_smp_ops __initdata = { |