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| author | Joseph Lo <josephl@nvidia.com> | 2013-07-03 13:50:38 +0400 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-07-19 20:08:05 +0400 |
| commit | ac2527bfc21739b77d687df1bfc4e973103fef7b (patch) | |
| tree | e217d872db97681d551caf07f38129a8f3fa473f /arch/arm/mach-tegra/sleep-tegra20.S | |
| parent | c04c77540a4f996ee94d0240bbae3a7512febd37 (diff) | |
| download | linux-ac2527bfc21739b77d687df1bfc4e973103fef7b.tar.xz | |
ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL
Adding a flag for tegra_disable_clean_inv_dcache to flush cache as LoUIS
or ALL. After this patch, the v7_flush_dcache_louis is used for CPU hotplug
and CPU suspend in CPU power down (e.g. CPU idle power-down mode) case. And
the v7_flush_dcache_all is used for CPU cluster power down (e.g. suspend to
LP2 mode).
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-tegra20.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-tegra20.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index e3f2417c420e..f87721d6e50d 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -191,6 +191,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency /* Flush and disable the L1 data cache */ + mov r0, #TEGRA_FLUSH_CACHE_LOUIS bl tegra_disable_clean_inv_dcache mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41 |