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| author | Joseph Lo <josephl@nvidia.com> | 2013-08-12 13:40:00 +0400 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-08-12 22:22:38 +0400 |
| commit | 5b795d051c61862cebf4f1d55edab6e9b3383b44 (patch) | |
| tree | c91e4a8aa4d89e65753ae383d9c9b3b99022f268 /arch/arm/mach-tegra/reset-handler.S | |
| parent | 20984c44b5a08620778ea14fa5807489170fd5ca (diff) | |
| download | linux-5b795d051c61862cebf4f1d55edab6e9b3383b44.tar.xz | |
ARM: tegra: add common resume handling code for LP1 resuming
Add support to the Tegra CPU reset vector to detect whether the CPU is
resuming from LP1 suspend state. If it is, branch to the LP1-specific
resume code.
When Tegra enters the LP1 suspend state, the SDRAM controller is placed
into a self-refresh state. For this reason, we must place the LP1 resume
code into IRAM, so that it is accessible before SDRAM access has been
re-enabled.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset-handler.S')
| -rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 34614bdf3f5b..f527b2c2dea7 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -182,6 +182,19 @@ after_errata: 1: #endif + /* Waking up from LP1? */ + ldr r8, [r12, #RESET_DATA(MASK_LP1)] + tst r8, r11 @ if in_lp1 + beq __is_not_lp1 + cmp r10, #0 + bne __die @ only CPU0 can be here + ldr lr, [r12, #RESET_DATA(STARTUP_LP1)] + cmp lr, #0 + bleq __die @ no LP1 startup handler + THUMB( add lr, lr, #1 ) @ switch to Thumb mode + bx lr +__is_not_lp1: + /* Waking up from LP2? */ ldr r9, [r12, #RESET_DATA(MASK_LP2)] tst r9, r11 @ if in_lp2 |