diff options
| author | Magnus Damm <damm@opensource.se> | 2011-05-17 14:39:22 +0400 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2011-05-24 07:28:56 +0400 |
| commit | 6776fba7e272ab236c789d58f290495d42684fe3 (patch) | |
| tree | 4e5f5a785bd7fee939b06343efd2aaab79147d35 /arch/arm/mach-shmobile | |
| parent | a63666c146f85a5ddcc3b2443d7c5888490e66b2 (diff) | |
| download | linux-6776fba7e272ab236c789d58f290495d42684fe3.tar.xz | |
ARM: mach-shmobile: Disable sh7372 RT side MSTP bits
Update the sh7372 clock code to set the RT side
set of MSTP bits to a fixed disabled state.
The sh7372 SoC contains two sets of MSTP bits,
one for the ARM (SYS) side, and one for the
SH4AL-DSP (RT) side. The actual clock associated
with the MSTP bit will only be stopped when both
sides have set the MSTP bit to disabled mode.
Some MSTP bits are enabled by default after
hardware reset, so this patch adjusts the code
to disable all MSTP bits associated with the RT
side to allow the SYS side to have full control.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/arm/mach-shmobile')
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh7372.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index fbca92cc530a..95b814aac556 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -44,6 +44,11 @@ #define DSI1PCKCR 0xe6150098 #define PLLC01CR 0xe6150028 #define PLLC2CR 0xe615002c +#define RMSTPCR0 0xe6150110 +#define RMSTPCR1 0xe6150114 +#define RMSTPCR2 0xe6150118 +#define RMSTPCR3 0xe615011c +#define RMSTPCR4 0xe6150120 #define SMSTPCR0 0xe6150130 #define SMSTPCR1 0xe6150134 #define SMSTPCR2 0xe6150138 @@ -654,6 +659,13 @@ void __init sh7372_clock_init(void) { int k, ret = 0; + /* make sure MSTP bits on the RT/SH4AL-DSP side are off */ + __raw_writel(0xe4ef8087, RMSTPCR0); + __raw_writel(0xffffffff, RMSTPCR1); + __raw_writel(0x37c7f7ff, RMSTPCR2); + __raw_writel(0xffffffff, RMSTPCR3); + __raw_writel(0xffe0fffd, RMSTPCR4); + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); |