diff options
| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2012-10-31 07:07:25 +0400 |
|---|---|---|
| committer | Simon Horman <horms@verge.net.au> | 2012-11-08 10:21:34 +0400 |
| commit | 9ee8008e99b36fff6a06c41a76594dd1b9a0677a (patch) | |
| tree | 5911821f1d4fc749987b41b4daa5cc82dd206440 /arch/arm/mach-shmobile/clock-sh7372.c | |
| parent | 9d626eccb1de90a310f3fb9bc5e8803706be1a95 (diff) | |
| download | linux-9ee8008e99b36fff6a06c41a76594dd1b9a0677a.tar.xz | |
ARM: shmobile: sh7372: sh7372_fsidivX_clk become non-global
Not only sh7372 but also many Renesas chip has FSI-DIV clock,
and we can share its sh_clk_ops.
To support common FSI-DIV clock, sh7372_fsidivX_clk
becomes non-global by this patch.
This is preparation for FSI DT support.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/clock-sh7372.c')
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh7372.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 430a90ffa120..18dcff7551c0 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -481,7 +481,7 @@ static struct clk_mapping fsidiva_clk_mapping = { .len = 8, }; -struct clk sh7372_fsidiva_clk = { +static struct clk fsidiva_clk = { .ops = &fsidiv_clk_ops, .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */ .mapping = &fsidiva_clk_mapping, @@ -492,15 +492,15 @@ static struct clk_mapping fsidivb_clk_mapping = { .len = 8, }; -struct clk sh7372_fsidivb_clk = { +static struct clk fsidivb_clk = { .ops = &fsidiv_clk_ops, .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */ .mapping = &fsidivb_clk_mapping, }; static struct clk *late_main_clks[] = { - &sh7372_fsidiva_clk, - &sh7372_fsidivb_clk, + &fsidiva_clk, + &fsidivb_clk, }; enum { MSTP001, MSTP000, @@ -583,6 +583,8 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk), + CLKDEV_CON_ID("fsidiva", &fsidiva_clk), + CLKDEV_CON_ID("fsidivb", &fsidivb_clk), /* DIV4 clocks */ CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), |