diff options
author | Paul Walmsley <paul@pwsan.com> | 2012-10-30 06:55:46 +0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-11-08 23:33:07 +0400 |
commit | d08cce6a1d6952a7774e4b61066d469c16d47a11 (patch) | |
tree | 13b56e022d8c8eaf720256b0de9dd9e1460a5d18 /arch/arm/mach-omap2/prm3xxx.c | |
parent | b6a4226c14001b0aa20b11c69190cb89d2237d3d (diff) | |
download | linux-d08cce6a1d6952a7774e4b61066d469c16d47a11.tar.xz |
ARM: OMAP2/3: PRM: add SoC reset functions (using the CORE DPLL method)
Add SoC reset functions into the PRM code. These functions are based
on code from mach-omap2/prcm.c. They reset the SoC using the CORE DPLL
reset method (as opposed to one of the other two or three chip reset
methods).
Adding them here will facilitate their removal from
arch/arm/mach-omap2/prcm.c. (prcm.c is deprecated.)
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/prm3xxx.c')
-rw-r--r-- | arch/arm/mach-omap2/prm3xxx.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 1fea656b2ca8..5435673ac9ce 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -123,6 +123,21 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) } /** + * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC + * + * Set the DPLL3 reset bit, which should reboot the SoC. This is the + * recommended way to restart the SoC, considering Errata i520. No + * return value. + */ +void omap3xxx_prm_dpll3_reset(void) +{ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, + OMAP2_RM_RSTCTRL); + /* OCP barrier */ + omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL); +} + +/** * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events * @events: ptr to a u32, preallocated by caller * |