summaryrefslogtreecommitdiff
path: root/arch/arm/mach-omap2/control.h
diff options
context:
space:
mode:
authorPaul Walmsley <paul@pwsan.com>2010-12-22 07:05:16 +0300
committerPaul Walmsley <paul@pwsan.com>2010-12-22 07:05:16 +0300
commit596efe4792c50163578578bd4fe470f97652aad7 (patch)
tree266074fe2cf349b8402db948a69b2822d5763b0e /arch/arm/mach-omap2/control.h
parent72e06d087204f3bc9acf281717b90ebf0b9731f7 (diff)
downloadlinux-596efe4792c50163578578bd4fe470f97652aad7.tar.xz
OMAP3: control/PM: move padconf save code to mach-omap2/control.c
Move the padconf save code from pm34xx.c to the System Control Module code in mach-omap2/control.c. This is part of the general push to move direct register access from middle-layer core code to low-level core code, so the middle-layer code can be abstracted to work on multiple platforms and cleaned up. In the medium-to-long term, this code should be called by the mux layer code, not the PM idle code. This is because, according to the TRM, saving the padconf only needs to be done when the padconf changes[1]. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> 1. OMAP34xx Multimedia Device Silicon Revision 3.1.x [Rev. ZH] [SWPU222H] Section 4.11.4 "Device Off-Mode Sequences"
Diffstat (limited to 'arch/arm/mach-omap2/control.h')
-rw-r--r--arch/arm/mach-omap2/control.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 4bfc1f0d974c..1ddc83bc2f84 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -359,6 +359,7 @@ extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
extern void omap3_ctrl_write_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
+extern int omap3_ctrl_save_padconf(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0