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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-13 03:00:54 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-13 03:00:54 +0300
commitdca1d9f6d7ae428c193f32bd3e9a4ca13176648b (patch)
tree02de8c3503c1c811754423d2fa3f3b4978044f6e /arch/arm/mach-mx2/clock_imx27.c
parent9ff99339447de403a46be5e3f23d0c794d540b06 (diff)
parent91e013827c0bcbb187ecf02213c5446b6f62d445 (diff)
downloadlinux-dca1d9f6d7ae428c193f32bd3e9a4ca13176648b.tar.xz
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (370 commits) ARM: S3C2443: Add set_rate and round_rate calls for armdiv clock ARM: S3C2443: Remove #if 0 for clk_mpll ARM: S3C2443: Update notes on MPLLREF clock ARM: S3C2443: Further clksrc-clk conversions ARM: S3C2443: Change to using plat-samsung clksrc-clk implementation USB: Fix s3c-hsotg build following Samsung platform header moves ARM: S3C64XX: Reintroduce unconditional build of audio device ARM: 5961/1: ux500: fix CLKRST addresses ARM: 5977/1: arm: Enable backtrace printing on oops when PC is corrupted ASoC: Fix S3C64xx IIS driver for Samsung header reorg ARM: S3C2440: Fix plat-s3c24xx move of s3c2440/s3c2442 support [ARM] pxa: fix typo in mxm8x10.h [ARM] pxa/raumfeld: set GPIO drive bits for LED pins [ARM] pxa/zeus: Add support for mcp2515 CAN bus [ARM] pxa/zeus: Add support for onboard max6369 watchdog [ARM] pxa/zeus: Add Eurotech as the manufacturer [ARM] pxa/zeus: Correct the USB host initialisation flags [ARM] pxa/zeus: Allow usage of 8250-compatible UART in uncompress [ARM] pxa: refactor uncompress.h for non-PXA uarts [ARM] mmp2: fix incorrect calling of chip->mask_ack() for 2nd level cascaded IRQs ...
Diffstat (limited to 'arch/arm/mach-mx2/clock_imx27.c')
-rw-r--r--arch/arm/mach-mx2/clock_imx27.c33
1 files changed, 18 insertions, 15 deletions
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 18c53a6487fa..0f0823c8b170 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -29,21 +29,23 @@
#include <mach/common.h>
#include <mach/hardware.h>
+#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
/* Register offsets */
-#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
-#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
-#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
-#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
-#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
-#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
-#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
-#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
-#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
-#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
-#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
-#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
-#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
-#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
+#define CCM_CSCR IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
+#define CCM_PCDR0 IO_ADDR_CCM(0x18)
+#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0 IO_ADDR_CCM(0x20)
+#define CCM_PCCR1 IO_ADDR_CCM(0x24)
+#define CCM_CCSR IO_ADDR_CCM(0x28)
+#define CCM_PMCTL IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
#define CCM_CSCR_UPDATE_DIS (1 << 31)
#define CCM_CSCR_SSI2 (1 << 23)
@@ -753,7 +755,8 @@ int __init mx27_clocks_init(unsigned long fref)
clk_enable(&uart1_clk);
#endif
- mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
+ mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+ MX27_INT_GPT1);
return 0;
}