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authorArnd Bergmann <arnd@arndb.de>2012-07-21 02:15:59 +0400
committerArnd Bergmann <arnd@arndb.de>2012-07-21 02:15:59 +0400
commit233de298cb44e7dd300cd68f5abd7f1a75561fd5 (patch)
tree2193094046036bec1a05883e63b1af5d9c067397 /arch/arm/mach-lpc32xx/clock.c
parent5e7c2c2f9785be62431270d48e2753e580d6a11c (diff)
parentc49a18308669a7c1bd61ddd4f575a88d49b0b852 (diff)
downloadlinux-233de298cb44e7dd300cd68f5abd7f1a75561fd5.tar.xz
Merge branch 'lpc32xx/core2' of git://git.antcom.de/linux-2.6 into next/soc
From Roland Stigge <stigge@antcom.de>: this LPC32xx core update (branch lpc32xx/core2) builds upon the previously provided lpc32xx/core-fixes. Basically including PWM support (for the PWM driver from Alexandre already in the pwm tree), and CPU ID. * 'lpc32xx/core2' of git://git.antcom.de/linux-2.6: ARM: LPC32xx: Add PWM support ARM: LPC32xx: Add PWM clock ARM: LPC32xx: Set system serial based on cpu unique id Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-lpc32xx/clock.c')
-rw-r--r--arch/arm/mach-lpc32xx/clock.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 8a4e7cb74ae1..f48c2e961b84 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -607,6 +607,19 @@ static struct clk clk_dma = {
.get_rate = local_return_parent_rate,
};
+static struct clk clk_pwm = {
+ .parent = &clk_pclk,
+ .enable = local_onoff_enable,
+ .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL,
+ .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN |
+ LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK |
+ LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) |
+ LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN |
+ LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK |
+ LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1),
+ .get_rate = local_return_parent_rate,
+};
+
static struct clk clk_uart3 = {
.parent = &clk_pclk,
.enable = local_onoff_enable,
@@ -1188,6 +1201,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
+ CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),