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authorMarcelo Tosatti <mtosatti@redhat.com>2012-10-30 01:15:32 +0400
committerMarcelo Tosatti <mtosatti@redhat.com>2012-10-30 01:15:32 +0400
commit19bf7f8ac3f8131100027281c495dbbe00cd5ae0 (patch)
tree270b97e3ca47c0f62a1babca2ae37f79a76a309c /arch/arm/mach-kirkwood/include/mach/bridge-regs.h
parent787c57c0fb393fe8a3974d300ddcfe30373386fe (diff)
parent35fd3dc58da675d659513384221349ef90749a01 (diff)
downloadlinux-19bf7f8ac3f8131100027281c495dbbe00cd5ae0.tar.xz
Merge remote-tracking branch 'master' into queue
Merge reason: development work has dependency on kvm patches merged upstream. Conflicts: arch/powerpc/include/asm/Kbuild arch/powerpc/include/asm/kvm_para.h Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'arch/arm/mach-kirkwood/include/mach/bridge-regs.h')
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index a115142f8690..5c82b7dce4e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -13,37 +13,37 @@
#include <mach/kirkwood.h>
-#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100)
+#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
#define CPU_CONFIG_ERROR_PROP 0x00000004
-#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
#define CPU_RESET 0x00000002
-#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define WDT_RESET_OUT_EN 0x00000002
#define SOFT_RESET_OUT_EN 0x00000004
-#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
#define SOFT_RESET 0x00000001
-#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
-#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0000
#define IRQ_MASK_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
-#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
-#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
+#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
#define L2_WRITETHROUGH 0x00000010
-#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
+#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
#define CGC_BIT_GE0 (0)
#define CGC_BIT_PEX0 (2)
#define CGC_BIT_USB0 (3)