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| author | Dirk Behme <dirk.behme@de.bosch.com> | 2016-02-19 09:50:12 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2016-02-28 10:55:26 +0300 |
| commit | bc3d8ede3a1d1336507d6a382764319cbbc9cf7a (patch) | |
| tree | cdda4de4756bc495f76a8eac60c6619bb2b1d34b /arch/arm/mach-imx | |
| parent | b4042a4c01b815f2fa63d237b9fe03204b7ab232 (diff) | |
| download | linux-bc3d8ede3a1d1336507d6a382764319cbbc9cf7a.tar.xz | |
ARM: imx: Do L2 errata only if the L2 cache isn't enabled
All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped. The write to the L2-Cache controller from non-secure
world causes an imprecise external abort. This is needed in
scenarios where one of the cores runs an other OS, e.g. an RTOS.
For the i.MX6 specific L2 cache handling we missed this check.
Add it.
Signed-off-by: Marcel Grosshans <MarcelViktor.Grosshans@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/system.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 93d4a9a39353..105d1ce4ed9d 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -106,6 +106,9 @@ void __init imx_init_l2cache(void) goto out; } + if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN) + goto skip_if_enabled; + /* Configure the L2 PREFETCH and POWER registers */ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val |= 0x70800000; @@ -122,6 +125,7 @@ void __init imx_init_l2cache(void) val &= ~(1 << 30 | 1 << 23); writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); +skip_if_enabled: iounmap(l2x0_base); of_node_put(np); |