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authorShawn Guo <shawn.guo@linaro.org>2013-10-17 06:07:09 +0400
committerShawn Guo <shawn.guo@linaro.org>2013-10-21 05:39:27 +0400
commit9ba64fe3eb461b95bf11436a13db0d9c79465514 (patch)
tree4ab4a7ee8c41bc2116b31799fb35f04c09411a53 /arch/arm/mach-imx/pm-imx6q.c
parentd48866fefdac239a4e02777e712aad60db9ee8a8 (diff)
downloadlinux-9ba64fe3eb461b95bf11436a13db0d9c79465514.tar.xz
ARM: imx: enable suspend for imx6sl
The imx6sl low power mode implementation inherits imx6q/dl one, and pm-imx6q.c can just work for imx6sl with some minor updates. Let's enable imx6sl suspend support by reusing pm-imx6q.c and use cpu_is_imxXX() to handle the those minor differences between imx6sl and imx6q/dl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/pm-imx6q.c')
-rw-r--r--arch/arm/mach-imx/pm-imx6q.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index f303b56f087c..aecd9f8037e0 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -144,6 +144,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
val |= 0x3 << BP_CLPCR_STBY_COUNT;
val |= BM_CLPCR_VSTBY;
val |= BM_CLPCR_SBYOS;
+ if (cpu_is_imx6sl()) {
+ val |= BM_CLPCR_BYPASS_PMIC_READY;
+ val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+ } else {
+ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+ }
break;
default:
return -EINVAL;
@@ -181,7 +187,8 @@ static int imx6q_pm_enter(suspend_state_t state)
imx_set_cpu_jump(0, v7_cpu_resume);
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
- imx_smp_prepare();
+ if (cpu_is_imx6q() || cpu_is_imx6dl())
+ imx_smp_prepare();
imx_anatop_post_resume();
imx_gpc_post_resume();
imx6q_enable_rbc(false);