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| author | Jens Axboe <axboe@kernel.dk> | 2011-10-19 16:30:42 +0400 |
|---|---|---|
| committer | Jens Axboe <axboe@kernel.dk> | 2011-10-19 16:30:42 +0400 |
| commit | 5c04b426f2e8b46cfc7969a35b2631063a3c646c (patch) | |
| tree | 2d27d9f5d2fe5d5e8fbc01a467ec58bcb50235c1 /arch/arm/mach-exynos4/clock.c | |
| parent | 499337bb6511e665a236a6a947f819d98ea340c6 (diff) | |
| parent | 899e3ee404961a90b828ad527573aaaac39f0ab1 (diff) | |
| download | linux-5c04b426f2e8b46cfc7969a35b2631063a3c646c.tar.xz | |
Merge branch 'v3.1-rc10' into for-3.2/core
Conflicts:
block/blk-core.c
include/linux/blkdev.h
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Diffstat (limited to 'arch/arm/mach-exynos4/clock.c')
| -rw-r--r-- | arch/arm/mach-exynos4/clock.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 851dea018578..86964d2e9e1b 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -520,7 +520,7 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 21), }, { .name = "ac97", - .id = -1, + .devname = "samsung-ac97", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 27), }, { @@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, }, { .clk = { - .name = "sclk_cam", - .devname = "exynos4-fimc.0", + .name = "sclk_cam0", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 16), }, @@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, }, { .clk = { - .name = "sclk_cam", - .devname = "exynos4-fimc.1", + .name = "sclk_cam1", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 20), }, @@ -1160,7 +1158,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650); + __raw_readl(S5P_VPLL_CON1), pll_4650c); clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; |