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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-03-19 16:07:34 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-30 03:49:10 +0400 |
| commit | dfbdd3d55403ebd29a355e907e53576ce57c6d96 (patch) | |
| tree | 823c0c626260f6005661843afc97342af883ed56 /arch/arm/mach-exynos/sleep.S | |
| parent | 24cb65feab42ac0cc26464ac4b7a38c0ab7ce173 (diff) | |
| download | linux-dfbdd3d55403ebd29a355e907e53576ce57c6d96.tar.xz | |
ARM: l2c: exynos: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-exynos/sleep.S')
0 files changed, 0 insertions, 0 deletions