diff options
author | Sekhar Nori <nsekhar@ti.com> | 2009-11-16 14:51:33 +0300 |
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committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-02-05 00:29:33 +0300 |
commit | 9a219a9ecf49ab156df4c18267ade4d468d9930e (patch) | |
tree | c71e664117603bbdf4eef09f1bb15fddccb86de4 /arch/arm/mach-davinci/clock.h | |
parent | d2de05827cce9438dfc61d5a4cf13b6ca82ebdee (diff) | |
download | linux-9a219a9ecf49ab156df4c18267ade4d468d9930e.tar.xz |
davinci: move PLL wait time values to clock.h
As suspend support is added, the code supporting
the suspend operation needs to bypass PLLs and
needs to access the same wait time values as the
PLL code in clock.c.
To facilitate this, move the PLL wait times to
clock.h where they can be accessed by suspend code.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/clock.h')
-rw-r--r-- | arch/arm/mach-davinci/clock.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index c92d77a3008d..eca4d9972225 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -53,6 +53,21 @@ #define PLLDIV_EN BIT(15) #define PLLDIV_RATIO_MASK 0x1f +/* + * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN + * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us + * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input + * is ~25MHz. Units are micro seconds. + */ +#define PLL_BYPASS_TIME 1 +/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ +#define PLL_RESET_TIME 1 +/* + * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 + * Units are micro seconds. + */ +#define PLL_LOCK_TIME 20 + struct pll_data { u32 phys_base; void __iomem *base; |