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authorSekhar Nori <nsekhar@ti.com>2009-11-16 14:51:33 +0300
committerKevin Hilman <khilman@deeprootsystems.com>2010-02-05 00:29:33 +0300
commit9a219a9ecf49ab156df4c18267ade4d468d9930e (patch)
treec71e664117603bbdf4eef09f1bb15fddccb86de4 /arch/arm/mach-davinci/clock.c
parentd2de05827cce9438dfc61d5a4cf13b6ca82ebdee (diff)
downloadlinux-9a219a9ecf49ab156df4c18267ade4d468d9930e.tar.xz
davinci: move PLL wait time values to clock.h
As suspend support is added, the code supporting the suspend operation needs to bypass PLLs and needs to access the same wait time values as the PLL code in clock.c. To facilitate this, move the PLL wait times to clock.h where they can be accessed by suspend code. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/clock.c')
-rw-r--r--arch/arm/mach-davinci/clock.c15
1 files changed, 3 insertions, 12 deletions
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index baece65cb9c0..0fa68c558320 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -376,7 +376,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
locktime = ((2000 * prediv) / 100);
prediv = (prediv - 1) | PLLDIV_EN;
} else {
- locktime = 20;
+ locktime = PLL_LOCK_TIME;
}
if (postdiv)
postdiv = (postdiv - 1) | PLLDIV_EN;
@@ -389,12 +389,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
__raw_writel(ctrl, pll->base + PLLCTL);
- /*
- * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
- * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
- * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
- */
- udelay(1);
+ udelay(PLL_BYPASS_TIME);
/* Reset and enable PLL */
ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
@@ -408,11 +403,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
if (pll->flags & PLL_HAS_POSTDIV)
__raw_writel(postdiv, pll->base + POSTDIV);
- /*
- * Wait for PLL to reset properly, OMAP-L138 datasheet says
- * 'min' time = 125ns
- */
- udelay(1);
+ udelay(PLL_RESET_TIME);
/* Bring PLL out of reset */
ctrl |= PLLCTL_PLLRST;