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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-03 02:04:12 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-03 02:04:12 +0400 |
| commit | a8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch) | |
| tree | 887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/kernel/iwmmxt.S | |
| parent | 168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff) | |
| parent | 2dc7667b9d0674db6572723356fe3857031101a4 (diff) | |
| download | linux-a8c4c20dfa8b28a3c99e33c639d9c2ea5657741e.tar.xz | |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
[ARM] 3541/2: workaround for PXA27x erratum E7
[ARM] nommu: provide a way for correct control register value selection
[ARM] 3705/1: add supersection support to ioremap()
[ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
[ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
[ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
[ARM] 3703/1: Add help description for ARCH_EP80219
[ARM] 3678/1: MMC: Make OMAP MMC work
[ARM] 3677/1: OMAP: Update H2 defconfig
[ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
[ARM] Add section support to ioremap
[ARM] Fix sa11x0 SDRAM selection
[ARM] Set bit 4 on section mappings correctly depending on CPU
[ARM] 3666/1: TRIZEPS4 [1/5] core
ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
ARM: OMAP: Update dmtimers
ARM: OMAP: Make clock variables static
ARM: OMAP: Fix GPMC compilation when DEBUG is defined
ARM: OMAP: Mux updates for external DMA and GPIO
...
Diffstat (limited to 'arch/arm/kernel/iwmmxt.S')
| -rw-r--r-- | arch/arm/kernel/iwmmxt.S | 27 |
1 files changed, 12 insertions, 15 deletions
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index a3bae95e536c..b63b528f22a6 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S @@ -271,30 +271,27 @@ ENTRY(iwmmxt_task_restore) /* * Concan handling on task switch * - * r0 = previous task_struct pointer (must be preserved) - * r1 = previous thread_info pointer - * r2 = next thread_info pointer (must be preserved) + * r0 = next thread_info pointer * - * Called only from __switch_to with task preemption disabled. - * No need to care about preserving r4 and above. + * Called only from the iwmmxt notifier with task preemption disabled. */ ENTRY(iwmmxt_task_switch) - mrc p15, 0, r4, c15, c1, 0 - tst r4, #0x3 @ CP0 and CP1 accessible? + mrc p15, 0, r1, c15, c1, 0 + tst r1, #0x3 @ CP0 and CP1 accessible? bne 1f @ yes: block them for next task - ldr r5, =concan_owner - add r6, r2, #TI_IWMMXT_STATE @ get next task Concan save area - ldr r5, [r5] @ get current Concan owner - teq r5, r6 @ next task owns it? + ldr r2, =concan_owner + add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area + ldr r2, [r2] @ get current Concan owner + teq r2, r3 @ next task owns it? movne pc, lr @ no: leave Concan disabled -1: eor r4, r4, #3 @ flip Concan access - mcr p15, 0, r4, c15, c1, 0 +1: eor r1, r1, #3 @ flip Concan access + mcr p15, 0, r1, c15, c1, 0 - mrc p15, 0, r4, c2, c0, 0 - sub pc, lr, r4, lsr #32 @ cpwait and return + mrc p15, 0, r1, c2, c0, 0 + sub pc, lr, r1, lsr #32 @ cpwait and return /* * Remove Concan ownership of given task |