diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-25 12:18:27 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-10-25 12:18:27 +0400 |
| commit | 1bc67188c3843b8e16caaa8624beeb0e2823c1f8 (patch) | |
| tree | 76299c9a161e2f179bf8bbd6c2b6c60191a9c76d /arch/arm/common/gic.c | |
| parent | 36b8d186e6cc8e32cb5227f5645a58e1bc0af190 (diff) | |
| parent | bdf4e9482360a3ddc1619efbd5d1c928ede8c3fa (diff) | |
| download | linux-1bc67188c3843b8e16caaa8624beeb0e2823c1f8.tar.xz | |
Merge branch 'for-linus' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'for-linus' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (81 commits)
ARM: 7133/1: SMP: fix per cpu timer setup before the cpu is marked online
ARM: 7129/1: Add __arm_ioremap_exec for mapping external memory as MT_MEMORY
ARM: 7136/1: pl330: Fix a race condition
ARM: smp: fix clipping of number of CPUs
ARM: 7137/1: Fix error upon adding LL debug
ARM: Add a few machine types to mach-types
ARM: 7130/1: dev_archdata: add private iommu extension
ARM: 7125/1: Add unwinding annotations for 64bit division functions
ARM: 7120/1: remove bashism in check for multiple zreladdrs
ARM: 7118/1: rename temp variable in read*_relaxed()
ARM: 6217/4: mach-realview: expose PB1176 ROM using physmap and map_rom
ARM: 7098/1: kdump: copy kernel relocation code at the kexec prepare stage
ARM: 7062/1: cache: detect PIPT I-cache using CTR
ARM: platform fixups: remove mdesc argument to fixup function
ARM: 7017/1: Use generic BUG() handler
ARM: 7102/1: mach-integrator: update defconfig
ARM: 7087/2: mach-integrator: get timer frequency from clock
ARM: 7086/2: mach-integrator: modernize clock event registration
ARM: 7085/2: mach-integrator: clockevent supports oneshot mode
ARM: 7084/1: mach-integrator: retire some timer macros
...
Diffstat (limited to 'arch/arm/common/gic.c')
| -rw-r--r-- | arch/arm/common/gic.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 3227ca952a12..666b278e56d7 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -180,7 +180,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, return -EINVAL; mask = 0xff << shift; - bit = 1 << (cpu + shift); + bit = 1 << (cpu_logical_map(cpu) + shift); spin_lock(&irq_controller_lock); val = readl_relaxed(reg) & ~mask; @@ -259,9 +259,15 @@ static void __init gic_dist_init(struct gic_chip_data *gic, unsigned int irq_start) { unsigned int gic_irqs, irq_limit, i; + u32 cpumask; void __iomem *base = gic->dist_base; - u32 cpumask = 1 << smp_processor_id(); + u32 cpu = 0; +#ifdef CONFIG_SMP + cpu = cpu_logical_map(smp_processor_id()); +#endif + + cpumask = 1 << cpu; cpumask |= cpumask << 8; cpumask |= cpumask << 16; @@ -382,7 +388,12 @@ void __cpuinit gic_enable_ppi(unsigned int irq) #ifdef CONFIG_SMP void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { - unsigned long map = *cpus_addr(*mask); + int cpu; + unsigned long map = 0; + + /* Convert our logical CPU mask into a physical one. */ + for_each_cpu(cpu, mask) + map |= 1 << cpu_logical_map(cpu); /* * Ensure that stores to Normal memory are visible to the |