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authorEnric Balletbo i Serra <enric.balletbo@collabora.com>2016-01-16 13:51:13 +0300
committerTony Lindgren <tony@atomide.com>2016-02-13 01:26:26 +0300
commitb328d9b86d5d22274a48b597f3226a8a21188cbc (patch)
treec2aad2c5465c5114b44443cc4fa06e4916732bc9 /arch/arm/boot
parent01c37be40fc35137a8b97e5176017958d57e401c (diff)
downloadlinux-b328d9b86d5d22274a48b597f3226a8a21188cbc.tar.xz
ARM: dts: am335x-sl50: Fix audio codec setup.
The MCLK is provided by an external clock of 24.576MHz. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/am335x-sl50.dts20
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts
index 9e1dac639fad..a676869536bc 100644
--- a/arch/arm/boot/dts/am335x-sl50.dts
+++ b/arch/arm/boot/dts/am335x-sl50.dts
@@ -67,12 +67,28 @@
default-brightness-level = <6>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* audio external oscillator */
+ tlv320aic3x_mclk: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>; /* 24.576MHz */
+ };
+ };
+
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM335x-SL50";
ti,audio-codec = <&audio_codec>;
ti,mcasp-controller = <&mcasp0>;
- ti,codec-clock-rate = <12000000>;
+
+ clocks = <&tlv320aic3x_mclk>;
+ clock-names = "mclk";
+
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
@@ -230,7 +246,7 @@
AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
- AM33XX_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
+ AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */
>;
};