diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-07-07 17:12:30 +0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-08-22 19:29:01 +0400 |
| commit | 070bd7e49171d1f4effef4d5edb718ba4743ec0a (patch) | |
| tree | ea364750db13603f8a3dda9d095d98d65b5d1470 /arch/arm/boot | |
| parent | eda5fe8bd70fbb430873382914a80ddbeb693e24 (diff) | |
| download | linux-070bd7e49171d1f4effef4d5edb718ba4743ec0a.tar.xz | |
ARM: dts: imx: Add the missing cpus node
To make it consistent with the other i.mx SoCs, let's add the cpus nodes.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/imx25.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx31.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 10 |
3 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index a69abaa87a26..bcd317172c0d 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -32,6 +32,16 @@ usb1 = &usbhost1; }; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + asic: asic-interrupt-controller@68000000 { compatible = "fsl,imx25-asic", "fsl,avic"; interrupt-controller; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 81167787785f..c34f82581248 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -20,6 +20,16 @@ serial4 = &uart5; }; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm1136"; + device_type = "cpu"; + }; + }; + avic: avic-interrupt-controller@60000000 { compatible = "fsl,imx31-avic", "fsl,avic"; interrupt-controller; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index a2115fa7c373..faceb22f2f65 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -35,6 +35,16 @@ spi2 = &cspi; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + tzic: tz-interrupt-controller@0fffc000 { compatible = "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; |